Former Strategic Sales & Business Development Manager at Intel:
"Google TPUs are trying to beat that performance per token with 30-40% less power requirement compared to Nvidia, so that's the main point... the performance per token will increase probably by 40x to 50x in two years."> Packaging Bottlenecks & Reticle Size Limits: TSMC's Chip-on-Wafer-on-Substrate (CoWoS) holds proven yields but is structurally capped at 6.5x to 7.5x reticle sizes. This creates a bottleneck as AI accelerators demand larger dies, more computing cores, and expanded high-bandwidth memory (HBM) stacking.> Intel's EMIB-T vs. TSMC: Intel's EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Via) offers projected yields above 90% and is estimated to be roughly 30% lower in cost compared to CoWoS. However, it remains commercially unproven against the 95% threshold required by major customers like Google. Furthermore, Intel faces packaging capacity constraints compared to TSMC's massive expansion. > Cost Breakdown: Advanced packaging costs typically run under $5,000 to $7,000, representing a fraction of a total system-on-chip (SoC) cost that can reach around $60,000 for advanced 3.5D setups. > Google's TPU Roadmap: Google is pursuing an aggressive trajectory targeting 30% to 40% lower power than Nvidia alongside a 40x to 50x increase in performance-per-token within two years. This push is driving faster dual-track adoption of 3.5D packaging solutions using small outline integrated circuits and Intel's EMIB-T. > Glass Substrates Timeline: Meaningful mass production of glass core substrates for high-volume AI accelerators is realistically expected to land around 2029. Consequently, near-term EMIB-T adoption relies on conventional organic substrates. > Foundry Preferences (14A vs. 18A): If Intel's packaging solutions successfully mature, large hyperscalers are more likely to lean toward Intel's 14A node rather than 18A. This preference is driven by 14A's power and area metrics being comparable to TSMC's N2P process, coupled with potential cost savings and relief from TSMC's allocation bottlenecks.$Alphabet(GOOGL.US) $Taiwan Semiconductor(TSM.US) $Intel(INTC.US)










