AMD’s new Venice processor and Instinct MI455X GPU are both in production at TSMC on 2nm, media report, adding AMD plans to have TSMC Arizona produce Venice as well (when fab ready). Both chips will use CoWoS-L advanced packaging.
Since CoWoS-L capacity remains tight, some orders for CoW to be done by ASE instead. AMD’s MI455X and subsequent AI accelerator chips will use SoIC packaging (for 3D hybrid bonding), which SoIC capacity seen hitting 15,000-20,000 wafers per month by end-2026. The MI455X uses SoIC to stack compute dies on top of 3nm Fabric and Cache dies (FCDs) before using CoWoS-L to connect them to HBM4 memory.SoIC: System on Integrated ChipsCoWoS-L: Chip on Wafer on Substrate-LSI (Local Silicon Interconnect) $AMD(AMD.US) $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US)Source: Dan Nystedt














