Arm

📢 𝗝𝗨𝗦𝗧 𝗜𝗡: $Astera Labs(ALAB.US) Astera Labs Launches New Leo Memory Solutions for Agentic AI Infrastructure

👉 𝗞𝗲𝘆 𝗛𝗶𝗴𝗵𝗹𝗶𝗴𝗵𝘁𝘀:

➤ 𝗔𝘀𝘁𝗲𝗿𝗮 𝗟𝗮𝗯𝘀 launches new 𝗟𝗲𝗼 𝗫-𝗦𝗲𝗿𝗶𝗲𝘀 and 𝗟𝗲𝗼 𝟮 memory controllers.

➤ Leo X-Series targets 𝗞𝗩-𝗰𝗮𝗰𝗵𝗲-intensive, long-context agentic AI inference workloads.

➤ Leo X-Series delivers up to 𝟲𝟮% faster time-to-first-token.

➤ Platform delivers up to 𝟮𝟮% more tokens per second.

➤ Leo 2 doubles 𝗺𝗲𝗺𝗼𝗿𝘆 𝗯𝗮𝗻𝗱𝘄𝗶𝗱𝘁𝗵 and capacity versus previous generation.

➤ New controllers support 𝗗𝗗𝗥𝟰, 𝗗𝗗𝗥𝟱, 𝗣𝗖𝗜𝗲 𝟲 and 𝗖𝗫𝗟 𝟯.𝟮.

➤ Leo 2 enables memory expansion, pooling, sharing, and 𝗗𝗗𝗥𝟰 reuse.

➤ Astera reports growing design wins across 𝗔𝗜 𝗹𝗮𝗯𝘀, hyperscalers, and neoclouds.

➤ New Leo products are 𝘀𝗮𝗺𝗽𝗹𝗶𝗻𝗴 𝘁𝗼𝗱𝗮𝘆 with hyperscaler customers.

➤ Development involved 𝗔𝗠𝗗, 𝗔𝗿𝗺, 𝗜𝗻𝘁𝗲𝗹 and major memory suppliers.

👉 𝗪𝗵𝘆 𝗧𝗵𝗶𝘀 𝗠𝗮𝘁𝘁𝗲𝗿𝘀:

➤ Agentic AI is rapidly increasing demand for 𝗺𝗲𝗺𝗼𝗿𝘆 𝗰𝗮𝗽𝗮𝗰𝗶𝘁𝘆 and bandwidth.

➤ Faster KV-cache access can improve 𝗔𝗜 𝗶𝗻𝗳𝗲𝗿𝗲𝗻𝗰𝗲 economics and responsiveness.

➤ Memory pooling and reuse could reduce expensive 𝗗𝗥𝗔𝗠 over-provisioning.

➤ Growing design wins could expand Astera's exposure to 𝗿𝗮𝗰𝗸-𝘀𝗰𝗮𝗹𝗲 𝗔𝗜 infrastructure.

👉 𝗘𝘅𝗽𝗲𝗿𝘁 𝗦𝘁𝗮𝘁𝗲𝗺𝗲𝗻𝘁𝘀:

𝗠𝗮𝘁𝘁 𝗞𝗶𝗺𝗯𝗮𝗹𝗹, Vice President and Principal Analyst at Moor Insights & Strategy:

“Agentic AI adoption is outpacing the industry's ability to provision memory for it, and that gap is widening every quarter," said Matt Kimball, vice president and principal analyst at Moor Insights & Strategy. "That growth is landing at the worst possible time for memory supply, with DDR5 tight and pricing climbing, so every gigabyte already deployed has to work harder. The new Leo X-Series and Leo 2 E and P-Series Smart Memory Controllers immediately address KV-cache-intensive AI workloads, improve memory utilization, and reliably reuse previously deployed memory across both AI and general-purpose cloud infrastructure, instead of simply buying more of it."

𝗧𝗵𝗮𝗱 𝗢𝗺𝘂𝗿𝗮, Senior Vice President, Compute Connectivity Group at Astera Labs:

“Agentic AI is where the economics of AI infrastructure are being decided, and those economics depend on putting every usable gigabyte of memory to work,” said Thad Omura, senior vice president, Compute Connectivity Group at Astera Labs. “The enhanced Leo family gives infrastructure providers purpose-built ways to connect memory to accelerators, CPUs, and hosts across the rack—turning previously deployed and stranded capacity into a resource that new AI and cloud workloads can use. We're seeing that translate into broader customer engagement across AI labs, hyperscalers, and neoclouds.”

𝗥𝗼𝗯𝗲𝗿𝘁 𝗛𝗼𝗿𝗺𝘂𝘁𝗵, Corporate Vice President, Architecture and Strategy at AMD:

“Agentic AI is increasing demand for balanced systems that can move and process more data without sacrificing efficiency. AMD EPYC processors deliver leadership performance, exceptional memory bandwidth and capacity, and high-speed I/O across the broadly deployed x86 platform. Our collaboration with Astera Labs around CXL extends that foundation, giving customers greater flexibility to scale memory-intensive AI and cloud workloads and improve infrastructure utilization.”

𝗘𝗱𝗱𝗶𝗲 𝗥𝗮𝗺𝗶𝗿𝗲𝘇, Vice President of Go-To-Market, Cloud AI, Arm:

“As AI infrastructure evolves, agentic AI, reinforcement learning and database workloads are driving demand for higher-capacity memory. Arm and Astera Labs are working together to pair Arm AGI CPU with Leo CXL Smart Memory Controllers, helping customers meet these growing requirements while maintaining scalable performance.”

𝗦𝗿𝗶𝗻𝗶 𝗞𝗿𝗶𝘀𝗵𝗻𝗮, Fellow at Intel Data Center Group:

"CXL was created to bring greater flexibility and efficiency to memory across the data center. Technologies like Astera Labs' Leo Smart Memory Controllers help turn that vision into reality, demonstrating how ecosystem innovation can help customers get more out of their AI infrastructure and support the next generation of data-intensive workloads."

𝗝𝗮𝗻𝗴𝘀𝗲𝗼𝗸 𝗖𝗵𝗼𝗶, Vice President of Product Planning Team at Samsung Electronics:

"We are contributing to the evolution of AI infrastructure through the development of CXL memory solutions designed to help address the growing memory demands of modern data centers. We are excited to collaborate with Astera Labs to help ensure our DRAM solution offer strong interoperability within the evolving CXL ecosystem, and remain committed to supporting a scalable, high-performance memory architecture for the AI era."